FIG. 1 schematically shows a cross section through the structure of a conventional elementary HEMT transistor system in an Oxz plane, the transistor being produced on a substrate 11. Conventionally, an insulating or semiconductor substrate 11 is used, for example comprising silicon (Si), silicon carbide (SiC) or sapphire (Al2O3), on which substrate a stack of at least two semiconductor layers is produced along the z-axis, said layers extending in the Oxy plane.
A first layer 12, denoted the buffer layer, has a wide bandgap (it is what is called a wide bandgap semiconductor material) and for example comprises a binary nitride compound material such as GaN or a material based on a ternary III-nitride compound (denoted a III-N) such as AlGaN or more precisely AlxGa1-xN.
A second layer, denoted the barrier layer 13, has a wider bandgap than that of the buffer layer 12. This layer comprises a material based on a quaternary, ternary or binary III-nitride compound (denoted a III-N) based on Al, Ga, In or B.
For example, with a GaN buffer layer, the barrier layer comprises AlxGa1-xN or In1-xAlxN, or a In1-xAlxN/AlN or AlxGa1-x/AlN sequence.
Depending on their aluminum content x, the bandgap widths of AlxGa1-xN and In1-xAlxN vary from 3.4 eV (GaN) to 6.2 eV (AlN) and from 0.7 eV (InN) to 6.2 eV (AlN), respectively.
The thickness of the barrier layer 13 is typically comprised between 5 nm and 40 nm and the thickness of the buffer layer 12 is typically comprised between 0.2 μm and 3 μm.
Additional layers may be present either on the surface of the device, or between the buffer layer and the barrier layer.
The buffer layer 12 and the barrier layer 13 are conventionally produced epitaxially by MOCVD or MBE. By way of example, mention may be made of a GaN-based buffer layer with a barrier layer based on AlGaN or InAlN, and more precisely based on AlxGa1-xN or d′InzAl1-zN, with x typically comprised between 15% and 35% and z typically comprised between 15% and 25%.
The junction between the buffer layer and the barrier layer forms a heterojunction 15 that also extends in the Oxy plane. The origin O of the coordinate system Oxyz is expressly placed in this plane.
A HEMT transistor conventionally comprises a source S, a drain D and a gate G, which are deposited on the top side 14 of the barrier layer 13.
The gate G is deposited between the source S and the drain D and allows the transistor to be controlled. The conductance between the source S and the drain D is modulated by the electrostatic action of the gate G, which is conventionally a Schottky contact or MIS (metal/insulator/semiconductor) stack, and the voltage VGS applied between the gate and the source controls the transistor.
A two-dimensional electron gas 9 (denoted a 2DEG) is located in the vicinity of the heterojunction 15. These electrons are mobile in the Oxy plane and have a high electron mobility μe, typically higher than 1000 cm2/Vs. In normal transistor operation, these electrons are unable to flow in the z-direction because they are confined in the potential well that forms in the Oxy plane in the vicinity of the heterojunction 15. The electron gas 9, which is confined in what is denoted the channel of the transistor, is therefore able to transport a current IDS between the drain and the source. Conventionally, a potential difference VDS is applied between the source S and the drain D, the source S typically being grounded, and the value of the current IDS depends on the voltage VGS applied between the gate G and the source S.
The transistor effect is based on the modulation of the conductance gm between the contacts S and D by the electrostatic action of the control electrode G. The variation in this conductance is proportional to the number of free carriers in the channel, and therefore to the current between the source and drain. It is this transistor amplification effect that allows a weak signal applied to the gate to be converted into a stronger signal picked up at the drain.
FIG. 2 shows the charge distribution in the vicinity of the heterojunction. Materials of the III-N family are highly electronegative. When two different compounds of this family are brought into contact, a fixed electrical charge that is either positive (σ+) (FIG. 2) or negative (σ−) appears at there interface. This fixed charge attracts mobile charges (electrons when it is positive such as in FIG. 2 or holes when it is negative). It is these mobile charges em that create a current when a voltage is applied between the drain and the source.
GaN is a semiconductor that, under conventional growth conditions, is doped with donor-type impurities (n-type impurities) (typically nitrogen vacancies). This type of defect does not allow a confinement of the electrons in the channel to be obtained when the voltage applied to the drain of the transistor becomes too high (typically higher than 10 V) and when the length Lg of the gate becomes too small (typically smaller than 0.25 μm). The electrons then flow through the buffer layer, this leading to a decrease in the conductance gm of the transistor.
The effect that this poor confinement of electrons in the channel has on the transfer function Log(IDS)=f(VGS) is to decrease the slope gm=ΔIDS/ΔVGS, such as illustrated in FIG. 3. This decrease is indicative of less effective modulation of the current by the gate.
Good transistor operation is obtained when curve 31 Log(IDS)=f(VGS) has a steep slope (such as illustrated in FIG. 3) at high constant VDS (for example 20 V) and for a small gate length (for example smaller than 0.25 μm). This steep slope, which is representative of a high transconductance gm, reflects the ability of the transistor to modulate high currents with a sufficient power gain at the operating point 30. In this case, the “pinch off” of the transistor is said to be good. Curve 32 illustrates a transistor exhibiting a poor “pinch off”. It is possible to quantify this value by a quantity called the subthreshold wing. A value thereof lower than 150 mV/decade of current is sought.
To obtain a transistor operation with a subthreshold wing lower than 150 mV/decade for the desired operating voltages it is necessary to compensate the initial n-type doping.
A first solution is to p-dope the (GaN or AlxGa1-xN) buffer by introducing acceptor-type impurities, for example by modifying the epitaxial growth conditions or by adding, during the growth, acceptor-type impurities. The impurity density introduced into the buffer is optimized to obtain the desired transistor behavior.
Compatible impurities are mainly carbon and iron but may also be magnesium, beryllium or zinc or any impurities known to be an acceptor center in GaN.
Typically, an excess of p-type impurities with respect to the n-type impurities of a few 1016 cm−3 to a few 1017 cm−3 allows a subthreshold wing lower than 150 mV/decade to be obtained for maximum operating voltages of 50 V (VDS) and gates of 0.15 μm length.
However, these impurities constitute deep centers. The expression “deep center” refers to an impurity the energy level of which is located more than 2 to 3 times the thermal activation energy (=3/2 kb*T) from the minimum of the conduction band in the case of an n-type impurity, or from the maximum of the valence band in the case of a p-type impurity. At room temperature, the thermal activation energy is about 40 meV. A center will therefore be considered to be deep if it is located at more than 100 meV from one of these extrema, this being the case for GaN doped with acceptor-type impurities.
These centers charge negatively when the transistor is biased and, as they are deep, do not discharge at operating frequencies higher than 1 MHz. This has the effect of decreasing the mobile charge present in the conductive channel, thereby decreasing current and increasing access resistance. It follows that the main drawback of this approach, in addition to generating dispersion, is that it decreases the efficiency of the transistor and the power that it is able to emit. The severity of this degradation in performance increases as the operating voltage VDS of the transistor increases (typically higher than 20 V).
This decrease in the amount of mobile charge, referred to as “current collapse”, is illustrated in FIG. 4. In this example the GaN buffer of the transistor is uniformly p-doped to a value of 5×1017 atoms/cm3.
Curve 40 illustrates a current/voltage characteristic of a transistor (produced at VGS=0V) that was not biased before the characteristic was measured.
Curve 41 illustrates a current/voltage characteristic of the transistor (produced at VGS=0V) after a stress taking the form of a voltage=VGS=−6V and VDS=40V was applied before the characteristic was measured.
It may be seen that the curve 41 of IDS as a function of VDS is modified with respect to the initial curve 40. The current/voltage characteristic is degraded, with, in this example, a relative variation of 60% in the current IDS (and therefore in the available power) at a voltage VDS of 5 V.
A second solution is to produce a composite buffer, for example a GaN/AlxGa1-xN buffer such as illustrated in FIG. 5, with a GaN channel. In this case, the negative piezoelectric charge that appears at the GaN/AlxGa1-xN interface 50 creates a potential barrier allowing the electrons to be confined in the channel. The AlxGa1-xN layer must contain a few percent of aluminum (typically 3% to 10%) to obtain a good confinement of the electrons for a maximum operating voltage comprised between 20 V and 40 V and a gate length smaller than 0.25 μm.
However, the thermal conductivity of AlxGa1-xN is lower than that of GaN by a factor comprised between 3 and 5 for the aluminum contents required for a good confinement of the electrons. The thermal resistance of the transistor is thus greatly degraded (multiplied by 2 to 3) and the power able to be emitted decreased by a factor of 1.5 to 3 (depending on the targeted applications) with this solution.
One aim of the invention is to mitigate the aforementioned drawbacks by providing a stack optimized for a HEMT transistor and allowing the HEMT transistor produced from this stack to exhibit good current/voltage characteristics, reflecting a good confinement of the electrons in the channel and a low current dispersion, including when the transistor must operate at high frequency (small gate dimensions) or at high drain voltages VDS.